I. Key Points of Parameter Specifications
- Layer number: 6–20 layers; HDI level: 1–3 stages or Any-layer.
- Materials: High Tg (≥170°C) with heat resistance for multiple reflow cycles; low Dk/low Df materials are options for high-speed applications.
- Microvias: Laser-drilled holes (0.075–0.15 mm), aspect ratio ≤1:1, copper-filled via plating.
- Line width/spacing: 3/3–2/2 mil; impedance: 50/100 Ω, ±10%.
- Surface finish: ENIG / Immersion Tin / OSP; thinner copper (1 oz) suitable for fine-pitch applications.
II. Key Points of Parameter Specifications
- Sequential lamination of micro-blind and buried vias enables any-layer interconnection.
- Copper-filled microvias support via-in-pad designs, enhancing density and reliability.。
- Thin dielectric + solid power/ground planes support high-speed signals.
III. Design Principle
- High Tg: Resistant to thermal stress from multiple reflow soldering cycles and resistant to thermal deformation.
- Short micro-via paths: shorten interconnects and reduce parasitic capacitance/inductance and signal loss.
- Symmetrical layer stack-up + matched-length differential pairs + precision impedance control: ensuring high-speed timing and signal integrity.
- Low Dk/Df materials: Further reduce high-speed signal loss.
IV. Solder mask characteristics
- LPI (Liquid Photoimageable) solder mask with fine-feature openings, compatible with microvias and fine-pitch pads.
- Uniform thickness, reliable insulation, and capable of withstanding multiple reflow cycles; primarily green solder mask, with black available upon request.
V. Application Areas
High-speed, high-density applications such as 5G communication base stations, network equipment/switches, semiconductor testing/carrier boards, high-speed communication modules, and servers/data centers.
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